Phase-locked loop (PLL) circuits are frequently utilized to lock an oscillator in phase with a reference signal. PLL circuits are often utilized within receivers in digital communication systems to generate a local clock signal that is phase aligned with an incoming reference signal. The phase aligned local clock signal facilitates the receipt and processing of data sent by a transmitter in the communication system.
Many communication systems utilize receivers that recover the clock signal from the incoming data sequence, typically using a PLL circuit. FIG. 1A shows a conventional PLL circuit 100 that includes a phase detector 105, a filter 110, a counter 115, a decoder 120 and a selector 125. In the conventional PLL circuit, the phase detector 105 compares the incoming data sequence and the output, P.sub.out, of the selector 125. The phase detector 105 generates an error signal that is representative of the phase difference of the reference signal and the output, P.sub.out, of the selector 125. The error signal is filtered by the filter 110 and applied to the counter 115, to indicate whether the phase of the output signal, P.sub.out, should be increased or decreased. The counter 115 typically generates a binary number, indicating which of a plurality of input signals, P.sub.0 through P.sub.N, should be selected as the output signal, P.sub.out, in order to achieve the desired phase adjustment, such that the output signal, P.sub.out, is phase aligned with the incoming data sequence. The decoder 120 converts the received binary value into a "high" logic value on the appropriate selector line, S.sub.i.
As shown more clearly in FIGS. 1B and 1C, the selector 125 increases or decreases the phase of the output signal, P.sub.out, by selecting an appropriate input signal, P.sub.0 through P.sub.N. The input signals, P.sub.0 through P.sub.N, are generated by a local multi-output oscillator (not shown), such that each input signal, P.sub.0 through P.sub.N, has the same frequency and a phase offset relative to each other equal to the inverse of the number of input signals multiplied by the oscillator period. In other words, if there are sixteen input signals, P.sub.0 through P.sub.15, each successive input signal has a phase difference of one-sixteenth the period. The frequency of the input signals, P.sub.0 through P.sub.N, is selected to be equal to the frequency of the transmitter (not shown) in the communication system, within a predefined tolerance. For a detailed discussion of an illustrative conventional receiver architecture and clock recovery, see J. Sonntag & R. H. Leonowich, "A Monolithic CMOS 10 MHz DPLL for Burstmode Data Retiming", pp. 194-195, International Solid-State Circuits Conference (1990), incorporated by reference herein.
A potential problem exists, however, for a PLL circuit that selects a clock signal from one of a plurality of locally generated phase-shifted oscillator signals. Specifically, as discussed further below in conjunction with FIGS. 2A through 2C, the output, P.sub.out, of the selector 125 may have a missing or severely degraded pulse, such as the pulse 175 shown in FIG. 1D, if the selector line inputs, S.sub.i, produced by the decoder 120, are changed during a transition of the selected clock phase or the desired clock phase. In addition, since conventional selector circuits 125 turn off the currently selected clock phase signal before activating the desired clock phase signal, neither clock signal drives the output signal, P.sub.out, during the transition period and the value of the output signal, P.sub.out, can vary unpredictably between a "high" logic value and a "low" logic value.
The pulse shown in FIG. 1D is frequently said to suffer from duty cycle distortion, since the likelihood of a "high" logic value and a "low" logic value are no longer each fifty percent (50%). As a result, the sampling of incoming data performed by the receiver, for example, using D-type flip-flops, may be corrupted. In addition, if the generated clock signal is utilized to clock the control logic 135 (FIG. 1 A) additional timing problems can be encountered.
Such duty cycle distortion can be avoided by operating the selector 125 at a much higher speed than the clock frequency, since the decoder 120 can change the values of the selector line inputs, S.sub.i, only when the selected input signal, P.sub.N, and its neighboring clock phases, P.sub.N.+-.1, are not in transition. When the clock frequency is approaching or exceeding the switching speed of the selector 125, however, the decoder 120 cannot guarantee that the values of the selector line inputs, S.sub.i, will be changed only when the selected input signal, P.sub.N, and the desired clock phase, P.sub.N.+-.1, are not in transition.